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CommonEvaluationPlatform
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CEP
The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.
BSD 3-Clause "New" or "Revised" License
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Compiling the Chipyard fails
#36
jordankrim
opened
6 days ago
3
Running Baremetal tests with Verilator 5.008 and CEP 4.5 fails
#35
jordankrim
opened
1 month ago
2
Finishing debugging optional inclusion of the LLKI
#34
bchetwynd
opened
1 month ago
0
Status of bareMetal test macroMix on v4.5 and v4.6
#33
jordankrim
opened
1 month ago
2
CHIPYARD: SD Interface on VCU118 times out
#32
bchetwynd
opened
2 months ago
0
CEP COSIM: All ISA tests fail when built on Ubuntu 22.04, running with QuestaSim 2023.4 (but pass on RHEL8)
#31
bchetwynd
opened
2 months ago
0
CEP ASIC: Update CEP ASIC build to be compatible with latest CEP release
#30
bchetwynd
opened
2 months ago
0
bfmTests/macroMix and bfm/srotErrorTest fail with xcelium
#29
bchetwynd
opened
2 months ago
0
Cannot compile the chipyard
#28
jordankrim
closed
1 month ago
23
SROT Wrapper does not support address spaces > 4GB
#27
bchetwynd
closed
2 months ago
1
CEP Co-Simulation using QuestaSim
#26
Omar-M-Yehia
closed
1 month ago
12
RTL-only build(s)?
#25
lmg260a
closed
6 months ago
1
README.md issues
#24
jordankrim
closed
2 months ago
0
Baremetal Test aesMacro fails due to SROT_aesonly_playback.h address out of range
#23
jordankrim
opened
9 months ago
0
COSIM: xcellium runs w/o proper timestamps
#22
bchetwynd
opened
11 months ago
0
bareMetal/regTest fails on two consecutive writes to SROT scratchpad registers only when L2 cache is present
#21
bchetwynd
opened
11 months ago
0
Upgrade to Chipyard v1.9.1
#20
bchetwynd
closed
2 months ago
0
Possible QuestaSim work-around?
#19
c-posada
closed
11 months ago
7
COSIM: bareMetal macro(n)Mix tests failing
#18
bchetwynd
closed
1 year ago
1
Cannot clone "CEP_Chipyard_ASIC" submodule
#17
WRansohoff
closed
1 year ago
2
IDFT - BFM macroMix test failure
#16
bchetwynd
closed
1 year ago
1
IDFT/DFT - Update source with less restrictive licenses
#15
bchetwynd
closed
1 year ago
1
Restore co-simulation dtmTest
#14
bchetwynd
opened
1 year ago
1
Debug FPGA Builds using more recent versions of Vivado (2021.1, 2022.1)
#13
bchetwynd
closed
2 months ago
1
auto-fir perl script does not run in Ubuntu 18.04
#12
bchetwynd
opened
1 year ago
1
COSIM: bare_malloc does not work as expected
#11
bchetwynd
opened
1 year ago
0
Fix Scratchpad assertion errors for sub-word access
#10
bchetwynd
closed
1 year ago
2
COSIM: Restore legacy tests
#9
bchetwynd
opened
1 year ago
0
Quest for the Unified Bootrom
#8
bchetwynd
opened
1 year ago
0
COSIM: XCellium *occasional* failures on RHEL7
#7
bchetwynd
closed
1 year ago
4
COSIM: Virtual Mode ISA Tests now failing after Chipyard bump to v1.7.0
#6
bchetwynd
opened
1 year ago
3
OPENTITAN: Up-rev opentitan version
#5
bchetwynd
opened
1 year ago
1
COSIM: FullBoot needs to be updated with new BAREMETAL_PRINTF switches
#4
bchetwynd
closed
1 year ago
1
VERILATOR: Baremetal tests on Verilator are only single-core
#3
bchetwynd
opened
1 year ago
0
VERILATOR: Update Verilator-based simulation to leverage FAST Memory Loading
#2
bchetwynd
opened
1 year ago
0
COSIM: Port "all" baremetal-tests to Verilator
#1
bchetwynd
opened
1 year ago
0