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你好,我是中国科学技术大学的学生。作为软件工程的作业,想做一个类似这个的系统,但是感觉现有文档没有有关框架的介绍,不知道怎么入手了解一下
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Currently, at synthesis boundaries all interface fields get turned into ports whose types are simply flattened bit vectors. This is rather annoying when trying to instantiate a Bluespec-synthesized m…
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Some keyword of SystemVerilog can be used as identifier in Veryl.
They will cause syntax error of transpiled SystemVerilog code.
So they should be checked by Veryl compiler.
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I see tool not able to understand the $system command and issue error as
Error: System task/function $system() is not defined by any module
How to invoke $system call from verilog ?
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With this 94-line test case
[test3.txt](https://github.com/user-attachments/files/16445114/test3.txt) (cut back from 2464 lines of production code) a couple of signals get declared as "signed" instea…
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I will use this issue to keep track of the status of my efforts to add cocotb support to VUnit and receive suggestions and feedback. I am new to VUnit (I haven't used it as a testbenching framework be…
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There seems to be a problem in the concat grammar. Given this simple verilog tests:
```
module test(input [4:0]b, input [4:0]c, output [8:0] a);
assign a = { b[1:0], c[2:1] };
endmo…
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Hi, I am seeking a waveform viewer that can be extended. I wondered if GTKWave supports the integration of external plugins.
The alternative idea is to fork/clone the repository and integrate the fu…
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**Type of issue**: other enhancement
**Impact**: Unknown
**Development Phase**: discussion
_I started writing this into a comment of #1361 but i figured out that a proper issue would be more app…
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Modern standard cell libraries include flops with asynchronous sets. For example, DC maps
```
module f(
input clk_i,
input rst_ni,
input set_i,
input q_i,
output reg q_o…