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The Nexys 4 DDR seems to have a Xilinx XC7A100T-1CSG324C with a -1 speed grade.
Currently ISE and Vivado are configured for -3.
Setting it to -1 currently does not close timing.
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In https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/canfd/src/xcanfd.c#L547 we have this comment:
```
/* Assign buffer number to user */
*TxBufferNumber = FreeTxBuffe…
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I've added a skid buffer between the UART RX FIFO and the external read interface, but as it currently is, with the FIFO configured as it is, I keep getting double the data. So I'm not sure what the …
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Thanks for sharing ,
I've tried in Vivado 2018.03 ,
by default run `generate.sh` , there's generation errors.
Could you help me for adapting your works on latest toolkit?
And, if you 're int…
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Hi, thanks for the repo and interesting paper.
While reading 5.2 Results and discovering Devcloud https://www.intel.com/content/www/us/en/developer/tools/devcloud/overview.html rather than whateve…
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I have 2 xilinx targets with MPSOC. multicore arm along side fpga. The 10G ethernet links the targets. This 10G ethernet is xilinx softcore on the fpga portion of SOC(system on chip). I have linux ru…
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Hi.
I was trying to use Vitis AI v1.3 released.
But I'm faced with problem to build docker image of CPU.
The error message is below:
**_---> Using cache
---> 4fdb8b2c11ab
Step 28/46 : RUN …
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OK guys, I'm interested.
after extensive Googling cannot locate Geophyte, which I presume is an Xilinx FPGA development system.
And, are the microSD cards vaporware at this point, or, can they also be…
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I'm using [MakeBlackbox](https://github.com/Xilinx/RapidWright/blob/60a571446d1bb78b9aba6ed497914631c2e7bc97/src/com/xilinx/rapidwright/util/MakeBlackBox.java#L35) in my design following the tutorial …
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Hello, my application scenario requires a DDR3 controller with axi interface, so I generated my DDR3 source code based on the stlv7325 development board. However, even if DDR3 initialization is succes…