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Greetings,
I'm trying to rebuild the images following the instructions from the link in Build from Source.
Rebuilding works but I can't seem to get networking fully working. I see the adapter on t…
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When I manually compile the build root no /dev/video0 is available and no files in /userdata/ is present. When using the images from google drive the camera does work. Do I need to enable something in…
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Hello, I'm trying to run ebpf programs (including `bcc` tools) inside kata containers to collect the guest kernel monitoring information, but I'm finding that it seems that the guest kernel doesn't ha…
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Hi everyone! I am relatively new using `litex`. In my first steps I just run the command line:
```
./terasic_de0nano.py --uart-name=jtag_uart --build --load
```
and then the process was completed …
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I could not find any reference to somebody trying this on the Altera brand of FPGA. (I did not want to buy another kind of FGPA and download yet another gigantic development environment.) The pre-bu…
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## Background
I've added a new platform Intel Stratix10 to OPTEE_OS which comes from Intel's socfpga chip. I would like to support OPTEE functionality based on this platform, ATF using Intel's offici…
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Usually CFU Playground is only supported for LiteX boards what exclude Altera/Intel boards, can I use other toolchains and frameworks to do this migration?
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```
rauc install http://10.0.0.10/bundles/update.raucb
installing
0% Installing
0% Determining slot states
20% Determining slot states done.
20% Checking bundle
20% Verifying signature
…
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I think it's time for an anchor issue to gather data for the Z-turn port since it is a very popular board.
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### Project Name
DRV32IMZicsr
### Description
DCD’s RV32IMZicsr RISC-V Core
### Homepage URL
https://www.dcd.pl/product-category/cpus/#riscv-2
### Repository URL
https://www.dcd.pl/product-cate…