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Hi,
- I met below error info when I tried to make prog in template proj. May I get help, thanks.
- I also plan to run it on XC7Z010-1CLG400C, so is there any reference guide for me ? Thanks.
…
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Hi...
I am trying to execute this code,
.
.
.
void print(const char*str){
while(*str){
uart_write(UART,*str);
str++;
}
}
void println(const char*str){
print(str);
uart_write(UART,…
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hello!
I'm having a problem implementing the core in vivado.
I have installed the riscv gnu toolchain and I am sure that it works ok, I modified the Makefile ($TOOLCHAINPREFIX).
I ran the makfil…
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Do you want access to the Fossil repository? Maybe this could be kept on a branch, of course that is up to you what you prefer! :-)
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Since the MISRA-C runtime has been merged in PR #3934 and discussed in RFC #3159 , I think now it's time to migrate uTVM standalone runtime ( introduced in PR #3567 )
### Rationale
* MISRA-C ru…
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I'm investigating an issue where a specific write-write-read sequence returns an incorrect result.
My LiteDRAM core is configured for Arty A7 with a 32-bit wishbone port.
I was able to reproduce th…
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It seems that CHERIoT SAFE on the Arty A7 fails to catch some spatial safety violations.
Here is a proof of concept:
```
diff --git a/examples/01.hello_world/hello.cc b/examples/01.hello_world/he…
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Some FPGAs feature internal temperature sensors.
It would be great to integrate these in LiteX and access them in Linux to read out the current operating temperature of the chip.
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Hi @tcal-x ,
I had a general doubt regarding synthesis of the Vexriscv core with the accelerator peripheral designed on an fpga.
Are the memory resources used in synthesis restricted to flip flops, BR…
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https://github.com/efabless/caravel_mgmt_soc_litex/blob/43d0ce33d331ee73d9dcebe197c6ce4da5909ecc/verilog/rtl/mgmt_core.v#L1774C31-L1774C31
This like appears to connect the SPI master controller `Da…