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Originally posted in SymbiFlow/symbiflow.github.io#2:
> @mithro
> https://developers.google.com/speed/pagespeed/insights/?url=symbiflow.github.io
>
> First paint is 2.6 seconds!
>
> * [ ] P…
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Currently the documented way to interact with the openroad python package is thru `openroad -python` (thru https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/odb/src/swig/python/main.cpp…
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The docs at https://python-symbiflow-v2x.readthedocs.io/en/latest/ don't link back to the repository.
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It seems that the `test_full_adder` for `ql-qlf` plugin fails due to a Yosys/ABC instability. Different builds from the same commit yields in different type and count of LUTs inferred for the `compara…
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With the assumption of .route file store the pips's names how to convert f4pag's result into dcp file and generate bit through vivado?
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We have;
- symbiflow-xc-fasm2bels
- symbiflow-xc7z-automatic-tester
- prjxray-bram-patch
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I have apend dsp to arch_def and generate a bits file which contains a DSP48E1 instantiation. But the bits does not work correctly on board. I don't know which step goes wrong. I want to verify the…
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@acomodi @mkurc-ant In a recent conversation @mithro suggested there was a way to run the symbiflow-examples toolchain using the surelog SystemVerilog front end. We are preparing to have students run…
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Setting the drive property in xdc file results in pin not being driven at all.
The cause is that the plugin sets the parameter to a string constant, while yosys expects an integer constant.
I al…
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Problem:
```
$ openFPGALoader -b arty_a7_35t /home/foo/git/external/f4pga-examples/xc7/counter_test/build/arty_35/top.bit
unable to open ftdi device: -4 (usb_open() failed)
JTAG init failed with…