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### `brew doctor` output
```shell
brew doctor
Please note that these warnings are just used to help the Homebrew maintainers
with debugging if you file an issue. If everything you use Homebrew for …
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git log
`commit f34d5ffb5ec5a9ca0356516ef4c1d4883f07ac96 (HEAD -> master, origin/master, origin/HEAD)`
pyhton3 python3 foboot-bitstream.py --revision pvt
```
Suffix successfully added to fi…
20Mhz updated
3 years ago
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I'm new with nix-darwin. I'm attempting to use it to manage homebrew packages but failing immediately
```
➜ darwin-rebuild switch --flake ~/.config/nix-darwin
user defaults...
setting up user laun…
amrox updated
2 months ago
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@daveshah1 [created a tool for generating Verilog to Routing XML files from verilog](https://github.com/SymbiFlow/symbiflow-arch-defs/tree/master/utils/vlog).
The goal is to eventually have fully …
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I see in j1a.v that the pin headers on the board are defined... with addresses defined under "IO PORTS" but I can't seem to set them:
> 255 $0020 io!
> ok
> $0020 io@ .
> 255 ok
> 255 $0010 io!
>…
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As the arachne-pnr github says: Arachne-pnr is not maintained anymore; use nextpnr instead, which is a complete functional replacement with major improvements.
The commands to use nextpnr-ice40 wit…
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I'm hitting
nextpnr-ice40 -q --lp384 --package cm36 --pcf tinyfpga_bx.pcf --json servant_1.0.2.json --asc servant_1.0.2_next.asc
terminate called after throwing an instance of 'nextpnr_ic…
olofk updated
4 years ago
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iceprog toplevel.bin in Murax of VexRiscv (gateware)
iceprog firmware.bin in picorv32
can do them both?
burn the gateware then firmware
then I can add instruction in Murax and modify riscv gcc com…
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Some of the iCE40 devices have a PLL disabled in certain chip packages. Current git head of Project IceStorm adds this information to the chipdb file.
1K ChipDB file:
```
.extra_cell 6 0 PLL
LOCKED …
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@cliffordwolf @FSMaxB @gordon-quad
We need more examples, what do you all think we need to add? (hoping we could brainstorm, I also have some time this weekend to create stuff)
Some ideas:
- C->Ver…