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Hello team,
I have added the trigonometric instructions on riscv-gnu-toolchain. Now I am specifically looking for the steps required/process to compile my workload in Spike and Gem5 with these newly …
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# Baremetal RISC-V Renode - Part 4: KOS Context Switch - blog.y2kbugger.com
[https://blog.y2kbugger.com/drafts/baremetal-riscv-renode-5.html](https://blog.y2kbugger.com/drafts/baremetal-riscv-renod…
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DISCLAIMER: this is a duplicate of a post I opened on Stackoverflow :
https://stackoverflow.com/questions/51825942/adding-new-instruction-to-riscv-32ima-bad-riscv-opcode
Hope to reach more/differ…
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The problem occurs for the assembly code generated by riscv-dv generator. The code generated y riscv-dv is assembled with gcc toolchain compiler:
`riscv64-unknown-elf-gcc -static -mcmodel=medany -fvi…
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How to test the RISCV kernel developed with Verilog using rv32ui in riscv-tests?Thank you!
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After installing the Ubuntu subsystem on Windows 10, I would like to build the riscv-tools so I can compile simple C programs and see the generated assembly code.
Following the instructions, the f…
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When I cross-compile RISCV assembly instructions in file.asm with "rustc 1.60.0-nightly (5e57faa78 2022-01-19) riscv64imac-unknown-none-elf" toolchain.
I got the following error:
```
error: instru…
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The default `fence` instruction with no parameters is the strongest form of barrier. But it also takes an optional set of flags to give fine-grained control over exactly what operations the fence is a…
jsgf updated
7 months ago
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### Technical Group
Architecture Test SIG
### ratification-pkg
Priv 1.11
### Technical Liaison
Allen Baum
### Task Category
Arch Tests
### Task Sub Category
- [ ] gcc
- [ ] binutils
- [ ] gdb…
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