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Hi,
I am getting the below error when running the command
`spike pk hello_world`
```
terminate called after throwing an instance of 'std::runtime_error'
what(): could not open pk (did you …
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I have compiled my application and linked it with an RTOS. Everytime I try to execute it on spike(am not using pk) I keep getting 2 errors: " terminate called after throwing an instance of 'trap_stor…
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Hi! I know that if I want to show the "perf counters" in a RV32I architecture, I can easily use the "Perf Cfu" variant. However, now I want to use a FPU supported RISCV CPU, namely that I cannot use …
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Hi!
The board manager already downloads gcc-7, but the compiler settings in platform.txt seem to be outdated. Right now it is not possible to compile for RISC-V.
![image](https://user-images.githu…
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in this section. a new phrase "may not be supported" is introduced. shouldn't it be unsupported optional?
==== RVI20U32 Mandatory Base
RV32I is the mandatory base ISA for RVI20U32, and is littl…
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Hi Neemann!
In order to fill memory contents I code in Verilog file:
initial $readmemh("RV32I_memory.txt",Memory);
I can with success the file in Digital, and export also the design file to Verilog…
j054n updated
2 years ago
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I am trying to build simulation, but I got this error:
ERROR: ../src/lowrisc_ibex_ibex_simple_system_core_0/ibex_simple_system.cc: In member function ‘std::__cxx11::string SimpleSystem::GetIsaStrin…
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Hi @aadomn,
Recalling [this observation](https://github.com/RustCrypto/block-ciphers/pull/184) and [your paper](https://eprint.iacr.org/2020/1123.pdf), specifically Figure 6 and the following parag…
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I have installed riscv-gnu-toolchain and riscv-tools, but when installing riscv-tools, riscv-pk was not successfully installed, so I installed riscv-pk separately, and the following error occurred dur…
CC-Hi updated
4 years ago
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In https://github.com/Mi-V-Soft-RISC-V/miv-rv32-bare-metal-examples/tree/main/driver-examples/miv-rv32-hal/miv-rv32i-systick-blinky there is a link to https://github.com/Mi-V-Soft-RISC-V/miv-rv32-docu…