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hello sir,
I am trying to directly test sha256_core.v without using sha256.v as the top-level module. I have written a testbench for it, but when I input the hexadecimal block value, I did not get th…
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I am part of a research group working on fuzzing Verilog designs. To this end we need a [combinational coverage](https://covered.sourceforge.net/user/chapter.metrics.html#example.metrics.logic) metric…
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### Describe the bug
We are trying to install this csi-driver on Kubernetes version 1.24.6, all nodes with OS Ubuntu 22.04. Installation from your manifests succeeds. Next, we create pvs and pod. A d…
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Any ETA for PKS 1.5 support ?
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If predictions have the same score, the current implementation of the metric will score them differently if they are submitted in a different order.
https://github.com/facebookresearch/isc2021/blob…
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In the Axi4 specs, section A3.3.1 "Dependencies between channel handshake signals" states that:
> The slave must wait for both `ARVALID` and `ARREADY` to be asserted before it asserts `RVALID` to i…
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https://github.com/gvsoc/gvsoc-core/blob/f2fa1fe4fd7eec65190aed5fe724c878fc524b89/models/memory/memory.cpp#L246C1-L246C58
To use the energy quantum's of the memory I need to comment this line out.
…
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**The problem:**
I am figuring out, how to test/simulate components that are hardcoded on the FPGA... For example...
Lattice iCE40UP5k FPGA *(package SG48)* has an internal SPI block that is har…
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# Debugging attiny85 code, part 3: Tracing with simavr · The Odd Bit
This is the third of three posts about using gdb and simavr to debug AVR code. The complete series is:
Part 1: Using GDB
A walkt…
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hi alex,
i run corundum cocotb-based testbench on cadence simulator (xrun).
my test env is:
conda3 with python 3.9
cocotb-1.60
corundum commit-tag: 76e18d2af8e8e97fdda4290114ee060cd15335c9
…