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zero-day-labs
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riscv-iommu
IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
Apache License 2.0
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fpga: Change default burst for xilinx ips
#34
CyrilKoe
opened
22 hours ago
0
not throwing error when pte.u bit is low in second stage translation
#33
mhayat-10xe
opened
3 days ago
0
G bit high in G-stage but not throwing error
#32
mhayat-10xe
opened
4 days ago
0
Virtual Address Translation Process Violation
#31
mhayat-10xe
opened
4 days ago
0
Error with Right Leaf Page Table Entry
#30
mhayat-10xe
opened
1 week ago
2
r_valid asserted before ar_ready
#29
mhayat-10xe
opened
1 week ago
0
Wrong cause_code if pte.a == 0 and dc.iohgatp.mode == 0
#28
mhayat-10xe
opened
1 week ago
0
Wrong triggering of pdt_walk_o signal when req_trans_i is 0
#27
mhayat-10xe
opened
2 weeks ago
0
Wrong cause_code if dc.tc.v == 0 when inclpc == 1
#26
mhayat-10xe
opened
2 weeks ago
0
Wrong cause_code if pc.ta.v == 0
#25
mhayat-10xe
opened
2 weeks ago
0
[RTL] Fix for issue number 20 and 22
#24
mhayat-10xe
opened
2 weeks ago
0
[RTL] Fix for issue number 17 and 18
#23
mhayat-10xe
closed
1 month ago
0
Not throwing error when DC is misconfigured with InclPC == 1
#22
mhayat-10xe
opened
1 month ago
0
fix(regmap): add missing include
#21
D3boker1
closed
1 month ago
0
Undefined cause_code when both ptw_error and wrap_error are high simultaneously
#20
mhayat-10xe
opened
1 month ago
1
Incorrect Rise of trans_valid Signal
#19
mhayat-10xe
opened
1 month ago
0
Wrong cause code if InclPC == 1 and pdte is misconfigured
#18
mhayat-10xe
closed
1 month ago
1
Wrong cause_code if InclPC == 1 and process directory entry is not valid
#17
mhayat-10xe
closed
1 month ago
1
[RTL] Fix for issue number 15
#16
mhayat-10xe
closed
1 month ago
0
Wrong cause_code during accessing PTE
#15
mhayat-10xe
closed
1 month ago
1
Not throwing error when pte.rsw bits are set
#14
mhayat-10xe
closed
1 month ago
0
Fixed the compilation error due to #12 PR
#13
mhayat-10xe
closed
1 month ago
0
[RTL] Fixes for issue number 10 and 11
#12
mhayat-10xe
closed
1 month ago
5
Wrong update of dc cache and error not raised when InclPC == 0 and dc.tc.pdtv == 1
#11
mhayat-10xe
closed
1 month ago
1
Wrong cause_code if dc.tc.v == 0 and at the same time dc.tc.gade == 1.
#10
mhayat-10xe
closed
1 month ago
1
[RTL] Fixes for unused and undriven RTL signals
#9
saadwaheed-10xe
closed
1 month ago
6
[FIX] Fixing errors raised by Synopsys Design Compiler
#8
maicolciani
closed
1 month ago
2
Exploring new opportunities with the recent rebase attempt
#7
yvantor
closed
2 months ago
1
First commit
#6
h-m-umar
closed
3 months ago
0
verilator check doesn't print anything
#5
jimaandro
closed
6 months ago
4
Question about verification
#4
jimaandro
closed
6 months ago
0
Some systemVerilog files missing?
#3
pcotret
closed
7 months ago
2
lint_checks - Mislabeled riscv_iommu ports
#2
pcotret
closed
1 year ago
1
Parameter pin not found: `axi_lite_req_t`
#1
pcotret
closed
1 year ago
1