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### OS
Windows
### Operating System version
Windows 10
### Visual Studio Code version
1.92.2
### ESP-IDF version
1.8.1
### Python version
3.11.9
### Doctor command output…
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With the software from "main" branch, the velocity is inverted and direction is decreased instead of increas
Set stepgen scale to 1000 pulses per millimeter and max working speed to 15 m/min. When …
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Hi, currently testing stuff with the following config :
AXI4 64 bits -> digilent nexys video DDR (16 bits physical, 128 bits access bus)
Things seems to mess up between lower and upper 64 bits of…
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I found that the icebreaker example SoC no longer fits in the Ice40: https://github.com/icebreaker-fpga/icebreaker-litex-examples/issues/14
I was told that I should report this to LiteX.
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Hi there!
I'm trying to boot with a Linux image created locally on a tang nano 20k, but I'm encountering an error that says "[LITEX-TERM] Got unexpected response from device 'b'E'" and the log stop…
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Hi,
I move the pulp project from fpga xcku115-flvd1924-1-c to fpga xczu15eg-ffvb1156-2-i.the clock of the cluster is griven by the soc_clk_rst_gen module same as the clk of the fc.
However,openocd c…
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Hello, we meet each other in a conversation of NeoRV32 Pull request, https://github.com/stnolting/neorv32/pull/194
I started a new repository for the ULX3S SDRAM setup: https://github.com/zipotron/ne…
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- [x] increase PCB size to accommodate future switch from 256 caBGA to 381 caBGA package
- [x] increase clearance around U8, U9, U11 (USB PHYs) to accommodate future switch from USB3343 to USB3320
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Coming back to this after a couple of months and installing new versions of everything (Litex/yosys/nextptr) from github, and now it won't compile (yosys error):
```
~/learn-fpga/LiteX$ python3 -m b…
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Dear Red Pitaya developers,
I've just tested one of the recent SD card images (red_pitaya_OS-v0.97-f9094af-release.zip) and found that the direct memory access in my MCPHA application doesn't work …