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https://halftop.github.io/post/Verilog_SPI/
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With the `sequence.hdl` example, the `_FSM` variable in the generated Verilog is never declared, so it defaults to a 1-bit `wire`. This results in it toggling between two states instead of going throu…
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Fault fails with wrong circt version.
```
def circt_opt_version() -> str:
circt_home = _circt_home()
circt_opt_binary = _circt_opt_binary(circt_home)
ostream = io.TextIO…
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**Test case**
```systemverilog
module test;
always_comb begin
// semantically illegal, but it is used to make lint error
a
y-kim updated
3 years ago
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Hi @danielholanda,
Your project was really great and it helped me a lot. I have successfully generated Verilog code as well as successfully creating a Quartus project. However, when synthesizing usin…
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What is the software you used ?
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I was wondering if this project could be used as a replacement for the Ethernet subsystem provided by Xilinx in Vivado. The Subsystem holds a MAC, Ethernet Buffer and PCS/PMA module. The MAC is not fr…
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### Feature Description
The following is a minimal example of what is not working:
`
typedef struct packed {
bit bit1;
} testtype_t;
module testmod;
wire testtype_t testwire; // fine
reg …
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## Expected behavior
When the cursor is on function in the below, it highlights both the brackets defined.
function
..
endfunction
However, when I place my cursor on the endfunction, it d…
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## System information
```
MyHDL Version: 0.12: experimental work on new converter
Python Version: 3.10+
```
I am working on a new converter approach to accommodate future target languages (first …
josyb updated
4 months ago