-
Add some option to report functions with template as single function in generated (html) reports
```
template
type sum( type x, type y) {
return x+y;
}
int main() {
auto result1 = sum(…
-
The IP-XACT standard allows for an optional mask element inside a field reset element. This is used to define which bits of the field have a known reset value. The absence of the mask element makes th…
-
Adding `always_latch` in [CG_MOD_neg.v](https://github.com/SiLab-Bonn/basil/blob/master/basil/firmware/modules/utils/CG_MOD_neg.v) and [CG_MOD_pos.v](https://github.com/SiLab-Bonn/basil/blob/master/ba…
-
### Checklist
- [x] Did you write out a description of the feature you want to see?
- [x] Did you look around for any related features?
### Feature Description
I would like to extend the fir…
ekiwi updated
2 years ago
-
Spinal version: v1.10.1
Simulation tool: Synopsys VCS 2018
Here's the simulation code:
```scala
SimTimeout(500 ms)
val perpPort = dut.socInst.logicMainInst.coreInst.io.d_perp
…
-
STR:
```
$ wget https://raw.githubusercontent.com/lowRISC/ibex/master/rtl/ibex_counters.sv
$ verilog_format ibex_counters.sv
rtl/ibex_counters.sv:65:1: syntax error, rejected "`else" (https://g…
-
您好,想请 顶层项目文件(类似于`Top.scala`,会导出一个基于SystemVerilog的SoC设计)的位置?
> 方便的话可否在README中说明?万分感激!
我注意到每个component有自己的`main()`,是否需要先导出SystemVerilog后手动组织?
-
evcd2vcd has problems in handling line feeds, for example:
```
$scope
module testbench.adder_instance
$end
```
will output
```
$scope
```
```
$var
port 1 [1] 270 segmentation f…
-
The problem as I see it is that if you ask vendors such as
Mentor/Siemen's Ray Salemi, FPGA Solutions Manager for Mentor's Questa,
the question, "Any word on Mentor supporting the new features in …
-
https://github.com/lowRISC/opentitan/blob/e9925bdf1464e9cec8ab8931c108cee4acb2709b/util/reggen/reg_top.sv.tpl#L655-L659
Shouldn't this code check `|(reg_be & ~PERMIT[i])`, not `|(PERMIT[i] & ~reg_b…