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**Test case**
```systemverilog
function int foo(logic [31:0] data);
return {
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## Input test case
1)
```systemverilog
localparam x = sin(1);
```
2)
```systemverilog
`b(sin());
```
Reproducer command:
```shell
verible-verilog-kythe-extractor --file_list_pat…
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Gist:
* extract symbol definitions and declarations and references
* establish use/definition links
* symbols would be properly scoped
Purpose:
* code navigation (IDEs)
* auto-completion
* al…
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Hi,
Questa gives an error as:
>> ** Error: ../src/lowrisc_dv_dv_lib_0/dv_base_env_cfg.sv(62): The actual (this.csr_addrs) and formal (csr_addrs) for a ref must be equivalent types.
I looked at …
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Example, we'd want something like:
```systemverilog
foo #(
.aaaa(111), // this line
.bb (22) // and this line
) bar (
.xx(x),
.y (yy)
);
```
Two-columns should be suff…
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See first line:
Want:
```systemverilog
typedef enum uint8_t {
kFoo,
kBar
} foo_t;
```
Got:
```systemverilog
typedef enum uint8_t{
kFoo,
kBar
} foo_t;
```
Fix needs to …
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Like so:
```systemverilog
if (!std::randomize(gnt_delay) with {
gnt_delay dist {
min_grant_delay :/ 1,
[min_grant_delay + 1 : max_g…
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## Input test case
Try to reduce the test down to a single demonstrative file.
```systemverilog
t=this.i();
```
## Describe what is wrong or missing
```
Crash Type: Segv on unknown addr…
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I just saw a CI failure on this PR: https://github.com/lowRISC/opentitan/pull/3048 in the 'Style-Lint DV Verilog source files with Verible' stage which was fixed simply by rerunning the CI without cha…
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### Description of the problem / feature request:
FAILED: Build did NOT complete successfully
### Feature requests: what underlying problem are you trying to solve with this feature?
was tryi…
admud updated
4 years ago