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I'm new to this repo, and failed to find the tests signatures, results. I think these were provided at some point .. What do I check/compare with my run results?
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Hi,
I'm making a schematic where I would like some I/Os to have a width that depends from a parameter.
I give the pin name a lab parameter like:
`name=p1 lab=sel_delay[RIPPLE_COUNTER_BITS-1:0]`
…
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Hi,
The Debian package has been removed form the next-stable Debian release.
https://tracker.debian.org/news/1376559/verilator-removed-from-testing/
Which means that at some point it will als…
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I am trying to modify the default python and run with the following command using verilator, and end up with the error below
_Command_
`SIM=verilator pytest -o log_cli=True test_mod.py`
_Erro…
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Info:
* Cocotb: 1.162
* OS: Windows 11, 64-bit
* Simulator: Icarus Verilog, Version 11 (2021-02-04), 64 bit
* Python: 3.9.7 via Anaconda
Whenever I try `print()` or `cocotb.log.info()` it does…
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I am using verilator as part of the rocket chip repo and had a question.
__Background__
I am generating the repository as a sub-component of a larger verilog project and have some control signals…
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1-We have a tech-mapped netlist. When I synthesize a netlist from Design Compiler it generates its sdf file too. So that we can run realistic simulations on it. However now we have auto-mapped netlist…
ghost updated
2 years ago
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Hi everyone, I'm a beginner with RISC-V and Chipyard.
I need to generate boom verilog code with dual issue active. I ran the command "~ /chipyard/sims/verilator # make CONFIG = SmallBoomConfig" but I…
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I'm using ubuntu-18.04;cocotb-1.6.2;python-3.6.9;verilator-4.221.
When I run the example,I found it stucked:
make -f Makefile results.xml
make[1]: 进入目录“/home/cx/桌面/cocotbtest”
verilator -cc …
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Hello,
I am trying to simulate the rocket chip Verilog using cadence simulator instead of vcs (cd vsim;make run)
I would like to know what to modify to do so! … is there an example of the makefrag a…