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Background: trying to replicate Lab 2 of EE290
I ran
`make CONFIG=GemminiRocketConfig `
to build a simulator for Gemmini but I do not see anything that tells me my verilog mesh is correctly …
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I am trying to compile and run the project but do not have access to VCS. Has anyone tried compiling with any other simulators?
The issues I have been running into seem related to the version of …
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Hello,
when trying to run make sim in ~lowrisc-chip/vsim (untether-v2.0), I get the following error:
```
alpha@alpha-VirtualBox:~/lowrisc-chip/vsim$ make sim
cd verilator && make -f Vchip_top…
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Author Name: **Andreas Olofsson**
Original Redmine Issue: 50 from https://www.veripool.org
Original Date: 2009-01-20
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What is the status of clock gating support? The documentation mention…
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Author Name: **Jie Xu** (@jiexu)
Original Redmine Issue: 757 from https://www.veripool.org
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When investigating to improve the performance of Verilator-based simulator model, I found the f…
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I get following error, when I test my design with very large arrays (**e.g. 131072x64 bits**):
```
** Fatal: accessed 32 bytes beyond global temp stack region
[0x55efa5e5a965] ../src/util.c:671 f…
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* the cocotb version used: 1.6.2
* the operating system and version (32/64 bit): Kubuntu 20.04.4 LTS, 64-bit
* the simulator and version (32/64 bit): Modelsim 2020.4, 32-bit
* the Python version:…
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Hello, I found out in your docs that eventually you would like to add simulation support to slang.
I was wondering what would be the roadmap / directions there? Also, where would you suggest
start…
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I'm seeing a relatively dramatic slowdown (25x--100x) compared to the old Chisel2 version of Rocket Chip. This is getting hit from both the Chisel3 version running a lot longer (10x the cycles) and th…
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## Steps to reproduce the issue
Use the folowing yosys script on the following .sv file:
```
read_verilog -sv synth_out.sv
write_verilog 0.v
```
Where `synth_out.sv` is
```
module synt…