-
The current implementation of encoder/mux utilities all result in a completely flat sequence of muxes. This is both:
1. Counterintuitive because [the Scaladoc specifically talks about "mux tree" ge…
-
The error message from firtool is drowned out. The line with the actual error message is an ```[info]``` line:
```
[info] Running CIRCT: 'firtool -format=fir -warn-on-unprocessed-annotations -veri…
-
在Ubuntu 22.04(amd64)环境下使用该工程，当chisel代码中加入Blackbox的addPath后，生成的verilog中会多出一行未注释的说明代码，导致无法通过verilator仿真
```
// ----- 8< ----- FILE "firrtl_black_box_resource_files.f" ----- 8< -----
build/build/dpi…
-
### Describe the bug
Any commit after `823e67a` is broken for tsx for me
tested on this example:
```tsx
import Image from 'next/image'
export default function Home() {
return (
…
-
Input:
```mlir
firrtl.circuit "Test" {
firrtl.module @Test() {
%child_ref = firrtl.instance child @Child(in in: !firrtl.ref)
%send_ref = firrtl.instance send @send(out dest: !firrtl.r…
-
The following FIRRTL program
```python
circuit top_mod :
module mod_0 :
input inp_a: UInt
output tmp18: UInt
tmp18
-
### Describe the highlighting problem
Certain portions of texts in certain files seem to get highlighted. I'd like to completely disable this sort of text highlighting. In other words, just have the …
-
I tried to build circt project according to README.md like:
```
$ cd circt
$ mkdir build
$ cd build
$ cmake -G Ninja .. \
-DMLIR_DIR=$PWD/../llvm/build/lib/cmake/mlir \
-DLLVM_DIR=$PWD/…
-
Hi, guys
I've encountered while testing hierarchical topology in Chipyard 1.8.1. I tried to run TestConfig66, 67, and 68, but encountered a FIRRTL error while running 67 and 68.(66 seems not have a…
-
I don't get these error messages from firtool displayed on the command line, only an exception dump when I run my design through chisel-circt:
```
circuit AptosNode :
^
:1:1: warning: Unhandled …