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I was trying to compile PICSimLab on my M1 MacBook Pro running macOS Monterey 12.4. After working around several hurdles, I eventually got things compiled (`picsim` (had to add `-framework OpenAL` to …
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Hi,
I have a question about vivado project.
During the make FPGA, an Ariane.xpr vivado project file was created in the FPGA folder. If I open this file, the file is empty, should this be the case? I…
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I'm working on making the project's codebase compatible with Intel/Altera Quartus for synthesis. Although Intel claims support for SystemVerilog-2009 it's not entirely true (I'm currently documenting …
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I've been implementing JTAG-DTM and DM lately, and have been wondering about automatic target identification and discovery methods. I skimmed through public discussions I could find around DM, DTM and…
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Support for Microsemi's Physical Design Constraint File (*.pdc file extension) for Libero SoC (for the following FPGA family: PolarFire, SmartFusion2, IGLOO2, RTG4, SmartFusion, IGLOO, ProASIC3, Fusio…
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#355 is brilliant, we we should do that. But can we also do something with https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps? It appears to em…
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Hi, Below CVEs are reported in the latest 1.6.19 image. These needs to be taken care as part of governance as memcached is being used across our k8s containers
CVE-2019-8457
CVE-2022-1304
CVE-202…
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Based on chipyard I generated a SoC with DRAM and SPIFlash, next I want to map this SoC to FPGA board. I will not use the JTAG interface for the time being, and directly read and load the executable f…
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Hi,
We are currently using latest HSS (0.99.33, release 2022.10) together with SoftConsole 2022.2 on an IcicleKit.
When programmed in Non Secure Boot Mode 1 (via SoftConsole), HSS boots successful…
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Hello, this is actually more of a question than a feature request. I did follow the discussion in the Ariane Cache support issue #61. One thing is still not clear to me.
Can I follow the same conf…