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Hello,
I'm trying to build litex bytestream with DDR3 support.
Previously, on-board DDR3 wa checked with GAO/simple example in sipeed github examples, so, should be operational.
But, when I load …
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It would be nice if the etherbone+litex functionality in wishbone tool was extracted into a library (*crate?*) that other tools could build on the top of.
Functionality which makes sense to me;
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I tried to run `./litex_setup.py --init --user -config=full` on a fully updated Arch box and during the installation of Git repositories step, I get the following error:
```bash
./litex_setup.py -…
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This issue aims to discuss moving to LiteX Hub packages. It was already executed in symbiflow-examples, and PRs are open for fpga-perf-tool and [symbiflow-arch-defs](https://github.com/SymbiFlow/symbi…
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I'm on an M1 Mac inside an Ubuntu virutal machine following [SymbiFlow Getting Started](https://symbiflow-examples.readthedocs.io/en/latest/getting-symbiflow.html). When I execute this step:
```
c…
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Could be easily done with https://github.com/enjoy-digital/litex_mister_test/issues/3 and https://github.com/enjoy-digital/litex_mister_test/issues/5 implemented.
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Using the script will be disabled because currently it does more harm than good.
This script was intended to make log analyzing easier. Unfortunately in many cases it hides crucial information from…
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Currently we have a hack which uses the crt0 from MiSoC/LiteX libbase - https://github.com/upy-fpga/micropython/blob/master/litex/Makefile#L60-L61
As we are using newlib, we really should be using …
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FastVDMA is available here https://github.com/antmicro/fastvdma
To integrate it with LiteX you have to generate Verilog code and wrap it in LiteX. Here is an example how a Verilog module can be wra…