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Hi, I am trying to run Linux in simulation. I followed the instructions in the linux.gen file but I get the following output.
INUX_SOC=yes EMULATOR=../../../main/c/emulator/build/emulator.bin VMLINUX…
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Spike appears to ignore the `--pc` argument, regardless of where it is placed on the command line:
```
user@Ondo:/opt/Xous/renode-ebreak-test$ /opt/Xous/spike/bin/spike -d --pc=0x80000000 -l -m1 -…
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**What will you do?**
Support LLVM [Global Instruction Selection](https://llvm.org/docs/GlobalISel/index.html) for a subset of [RISC-V Vector Extension](https://github.com/riscv/riscv-v-spec/blob/m…
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**Is your feature request related to a problem? Please describe.**
kinda
**Describe the solution you'd like**
add custom ram and storage options
maximum amount of storage - 50GB
maximum amoun…
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A naive question, I want to modify CHERI RISC-V ISA by adding an crypto instruction so compiler should also need to be modified to generate instruction. Is there any document of workflow that how many…
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Trying to run bbl on a rocket core sans FPU. I manually added the "-msoft-float" flag in the Makefile and compiled. BBL starts up and prints the logo, but then hangs after that.
Inspecting the instru…
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The comparison operator for "BLTU" in riscv.c (l. 91) should be "=" (this line is identical to the "BGE" line below it except for the instruction name):
if (opcode==0b1100011 && funct3==0b110) { if…
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Currently semu does not support graphics rendering.
I think VirtIO GPU with 2D mode might be a good starting point to go.
Later we can then emulate mouse and keyboard for more sophisticated featu…
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I am using RISCV-ISAC to generate the add instruction coverage. I found that some checkpoints in CGF are 0, but it is obvious from the assembly file that this constraint is satisfied. Is this normal?…
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Tried to compile som fir becnhmark test and with this instruction :
riscv64-unknown-elf-gcc -I/home/edgar/Desktop/RISCV_FOLDERS/rocket-chip/riscv-tools/riscv-tests/build/../benchmarks/../env -I/hom…