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Hi Neemann!
In order to fill memory contents I code in Verilog file:
initial $readmemh("RV32I_memory.txt",Memory);
I can with success the file in Digital, and export also the design file to Verilog…
j054n updated
2 years ago
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Hi,
While executing the `make clean simulate verify postverify XLEN=32 RISCV_DEVICE=Vi` command I am encountering following error for work/rv32i_m/Vi/VADC-VIM-SEW16_LMUL1.*
`Error (SIGNATURE_DUMP_…
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In https://github.com/Mi-V-Soft-RISC-V/miv-rv32-bare-metal-examples/tree/main/driver-examples/miv-rv32-hal/miv-rv32i-systick-blinky there is a link to https://github.com/Mi-V-Soft-RISC-V/miv-rv32-docu…
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When I build this toolchain locally (./configure --prefix=$INSTALL_DIR --with-arch=rv32i --with-cmodel=medlow --with-multilib-generator="rv32i-ilp32--;rv32ima-ilp32--") I notice in the output there a…
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I have been playing with riscv-formal for checking one of our small processors, and I came across a few issues where the documentation does not appear to match what the checks are actually doing. Our …
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Hi! I think there is a problem in riscv-trunk when compiled with -O1 option. I attached an example in c and the generated assembly.
I compile with:
/.../clang -O1 -target riscv -mriscv=RV32I test.c …
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I believe its legal for an implementation to have support for both : E and I base extensions. But section 28.2 in the spec says :
```
RISC-V ISA strings begin with either RV32I, RV32E, RV64I, or …
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Specifically ALUSrc control signal. Somehow it accepts `(~6).(~4) + (~6).(~5).(4)` but not `(~6).(~4) + (~6).~(5)`, though they are the same in boolean logic.
rjlv2 updated
5 years ago
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The command to generate floating point assembly tests in the fadd.d_b1-01.S file[https://github.com/riscv-non-isa/riscv-arch-test/blob/main/riscv-test-suite/rv32i_m/D/src/fadd.d_b1-01.S](https://githu…
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Dear maintainers,
As you may know, Control State Register (CSR) is removed from base instruction in RV32I and RV64I version 2.1. So, we should remove the use of CSR related instructions in rv32ui a…