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In https://github.com/The-OpenROAD-Project/OpenROAD/issues/580 we are chasing an issue where TritonRoute has problems with pin access on some standard cells (in this particular case `sky130_fd_sc_hd__…
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### Description
Following a tutorial I got an error in interactive mode. Any step of a tutorial which requires an interactive mode do not work.
### Expected Behavior
On the command
```
or_gu…
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Having a clear method of tracking what version of `extra_be_checks` is included in `mpw_precheck` is needed.
Current commit of `extra_be_checks` is `a60939f2844da06a8907d04c3368d17de5b1db84` and co…
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## Expected Behavior
`klayout` starts w/o error message.
## Actual Behavior
When klayout is started with `klayout -e -nn $PDKPATH/libs.tech/klayout/tech/$PDK.lyt -l $PDKPATH/libs.tech/klayout…
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A large number of the verilog files in the standard cells are automatically generated from a `definition.json` file.
### Non-generated files
- `sky130_fd_sc_XX__XXXXXX.specify.v`
- `sky130_fd…
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The output of `open_pdks` is non-deterministic -- IE the exact same input does not produce the exact same output.
This is demonstrated by the PDK being built every 30 minutes and published in the r…
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Hi @d-m-bailey
I am trying to run CVC on the spice extracted from the gds. CVC first complained on missing models:
```
ERROR: No model match sky130_fd_sc_hd__a21oi_1/X4 X sky130_fd_pr__pfet_01v…
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### Description
I am using the latest commit on master:
```
my_openlane2 = let
src = pkgs.fetchFromGitHub {
owner = "efabless";
repo = "openlane2";
…
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MPW-8 slot-015 uses `sram_2kbyte_1rw1r_32x512_8`.
The `openram_dff` cell has both `VDD` and `vdd` labels and `GND` and `gnd` labels on the layout.
This extracts to
```
.subckt EL_G3_sky130_f…
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Hi,
I have created a circuit schematic in xschem using the sky130 PDK, and am trying to use netgen to generate a ".sim" file from xschem's created ".spice file". The intended purpose of the ".sim"…