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Clash 1.6.4 (and 1.6.3) compiled against ghc 8.8.4 on debian unstable synthesizes verilog fine for my code, but 1.6.4 compiled against ghc 9.0.2 fails on the same synthesis. Same machine, same everyth…
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![image](https://github.com/Digital-EDA/Digital-IDE/assets/102217741/5e817c41-c54d-409c-be36-576efb0a299a)
类似于这种检索方式,图片来自Verilog-HDL/SystemVerilog/Bluespec SystemVerilog插件的例化方式。
当前例化方式直接列出来所有v文件的方式,…
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Hi,
I'm trying to use hdlConvertor to discover all the files I need in my file list. (If someone has already done this please let me know :) )
So far I'm checking the error messages for missing i…
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The simplest possible block RAM, one that is initialized to all zeroes:
```
import Clash.Prelude
type Addr = Unsigned 13
type Value = Unsigned 8
topEntity
:: Clock System Source
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@umarcor @LarsAsplund @JimLewis @eine @suzizecat @Paebbels @nfrancque I have been talking a bit with @qarlosalberto about potentially creating a sphinx builder/autodoc plugin for HDL, although I'm mor…
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**What is your question?**
DISCLAIMER: This is a question and suggestion. let me know if you want me to seperate the suggestion into a seperate issue for tracking my feature request.
I actively us…
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#574 の日本語版
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# VerylによるRTL設計の漸進的な進化
VerylはSystemVerilogの代替言語として設計されたハードウェア記述言語です。特に既存のVerilog/SystemVerilogコードベースを漸進的に改善することに着目しています。
「漸進的」とは既存のコードベースの一部を徐々にVerylに置き換えていくことが可能であることを意味します…
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### Check for existing issues
- [X] Completed
### Language
SystemVerilog
### Tree Sitter parser link
https://github.com/tree-sitter/tree-sitter-verilog
### Language server link
ht…
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(Note that I program in SystemVerilog, not VHDL)
Hello,
I'm trying to simulate your 'ym2149_audio.vhd' in ModelSim. Your core appear to properly receive my command and the PCM out does change …
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Hi,
I'm a Computer Science Engineering student in Spain and I'm using RIPES for my final degree's project. My aim is to add a new processor model, which is described in System Verilog.
I am follow…