-
**Description**
After compiling ALL Xilinx libraries I discovered that a lot of in the XIlinx libraries available components are not compiled in the GHDL libraries.
Maybe I'm doing something wrong? …
-
Hello
I'm interested in this project, since am working on a commercial version of a FIRRTL Simulator implemented in Scala for large SoC designs. Our goal is to support Rocket and Boom simulations …
-
There doesn't seem to be a way to identify `reg` type in UHDM model. The type is modeled as `logic_typespec` but there's nothing in the model to differentiate it with regular `logic` type.
```
mod…
-
Thanks a lot for this great project! @alexforencich @rodrigomelo9
I am trying to run the `axi-verilog` designs using `verilator`, however, this library does not seem to be compatible with verilator…
-
# Issue: Develop Testbench Environment for Testing CSI-2 Camera Model in Cocotb
## Description
The goal of this issue is to develop a testbench environment for testing a CSI-2 camera model using…
-
Clash 1.6.4 (and 1.6.3) compiled against ghc 8.8.4 on debian unstable synthesizes verilog fine for my code, but 1.6.4 compiled against ghc 9.0.2 fails on the same synthesis. Same machine, same everyth…
-
What would you like added/supported?
**typedef derived from type defined inside interface**
Can you attach an example that runs on other simulators? (Must be openly licensed, ideally in test_re…
-
The Bluespec compiler emits Verilog which makes **[Yosys](https://github.com/yosyshq/yosys)** somewhat unhappy:
```
1.3. Executing Verilog-2005 frontend: /tmp/yosys-bsv-v-QxaOnJ/keccak.v
Parsing …
-
Hello,
I am using the most current version of CIRCT and I am having issues getting even some "basic" RTL to work properly. The behavioral simulation in Vivado 2021.2 is working correctly, but the p…
-
Sv2v version 0.11.0 is represented by vectors when converting the structure, and the name of the field cannot be seen in the converted Verilog code, resulting in poor readability, can the name informa…