-
Hi it seems the changes needed for 2021-2023 is minor.
```
diff --git a/examples/alpha250/adc-dac-dma/block_design.tcl b/examples/alpha250/adc-dac-dma/block_design.tcl
index e28f2090..edb64099 10…
-
While compile the project mentioned in [the problem](https://github.com/ghdl/ghdl/issues/1307) and happened errors! What's wrong with this?
command as mentioned in the above problem :
`yosys -m ghdl…
-
Hello,
In Coverity's report (https://scan4.coverity.com/reports.htm#v40445/p11439), there are two issues flagged inside Xilinx platform code. The related CIDs are 273588 and 273589.
For CID 2735…
ghost updated
5 years ago
-
Not sure if this is a great title, so I can change it if necessary. I have been having an issue recently, where I have _huge_ delays when my editor (Neovim) goes to complete something. I boiled it dow…
-
https://github.com/Xilinx/Vitis-Tutorials/blob/58e54fa809d6cdb4a59212055aa1d23e051f7ec7/Getting_Started/Vitis/Part4-embedded_platform.md?plain=1#L18
The image link from this tutorial is broken.
-
Hello,
I'm wondering if parts of this project can be used to control the Xilinx soft PCIe PHY ([PG239](https://www.xilinx.com/content/dam/xilinx/support/documentation/ip_documentation/pcie_phy/v1_0…
-
is there any .xml file available to build a debian system on a Xilinx ultrascale+ mpsoc?
-
After meeting together we found that we will not be able to meet the assigned time for having everything updated on the wiki pages. We have some items that came up that will require additional resear…
-
## Steps to reproduce the issue
[minitest_bram_36.zip](https://github.com/YosysHQ/yosys/files/4298887/minitest_bram_36.zip)
Run `make bram.edif` to call yosys
Run `make bram_vivado.bit` to call…
-
Hello. I am trying to get PyOpenCL to work on my Xilinx FPGA board. I followed all the steps from [nachiket](https://github.com/nachiket) and I got to the part where the environment variables are set,…