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Hi,
I've currently built a few KunaiGCs and am ready to perform the flashing steps. The CPLD seems straghtforward, although I am not sure which jedec file I should be using to flash, as that is not…
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Hi, could you please develop the environment OrCAD v10.5 For Linux 64-Bit. I believe OrCAD v10.5 is just fine for Linux.
The below products are just fine:
Capture CIS
Layout Plus
PSpice A/D
…
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We have started to do some work but we didn't have an issue for it so I'm creating one.
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Sorry, if this is an offtopic, i'll move it to maillist if it's so. This is just common suggestions about "full metal runtime.js/nodejs" related to this #42 and this #43 issues.
Besides all feature…
danxn updated
9 years ago
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Author Name: **Peter Gerst**
Original Redmine Issue: 1369 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
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Verilator does not throw error / warning on continuous …
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@shenki has had the repl loop working in QEmu.
@mithro has had the repl loop working on Opsis hardware.
@Kathatosada got repl loop working on the MimasV2 at Linux.conf.au
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We're currently trying to get a Xilinx DRAM controller (MIG) to work. In the core file, we include the IP-XACT file (*.xci), which then causes Vivado to generate the code for this IP. Right now, it [l…
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Hi,
I'm trying to flash a standalone Xilinx xc6slx25 through a Digilent HS2 cable. From browsing previous issues I learned that I need a dedicated spiOverJtag file and specify the --fpga-part for…
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Compiling by ISE finished with error:
ERROR:HDLCompiler:1195 - "D:\projects\github\CoreAmstrad\BuildYourOwnZ80Computer\simple_DSK.vhd" Line 793: Prefix of attribute high is not a type mark
The li…
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## Issue Description
`memory_libmap` pass in Yosys 0.18 and newer would synthesize LUTRAMs unsupported by nextpnr including:
- RAMS32 (manually instantiated)
- RAMD32 (manually instantiated)
- R…