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Hello!
When I use the DRC checking tool, it runs very slowly.
And command '**threads(8)**' doesn't work.
Can you give an example of how to use it?
Thank you!
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### Description
Hi everyone, I am trying to use openlane and skywater pdk to synthesize my ALU design . When start the flow my config.tcl file i get the following error:
[INFO]: Running Synth…
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### Discussed in https://github.com/The-OpenROAD-Project/OpenLane/discussions/1346
Originally posted by **IngYordiDelgado** September 9, 2022
i tried to test a project with multiple verilog f…
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If one set_max_delay constraint terminates (-to) on combinational cell where another one starts (-from) one or both of these constraints are lost. I'm attaching a simple example. Two first SDC lines s…
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## Description
I have a design that I'm trying to build using OpenLane, but it only passes once I run the design through a yosys synth first.
The design can be found [here](https://github.com/Fras…
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Hello, is the GDS of the test chip available or going to be available? Optical images on their own are not helpful in some scenarios. Thanks
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Hi. I'm using Innovus for PnR, and precheck for DRC check. I'm having difficulty passing a GDS with SRAM through the "Klayout minimum metal density area clearance" check; It gives 1200 errors, all in …
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PG ID 1320: When reading the gds file, magic terminates with no error message.
```
user@ciic-cvc:~/mpw-7/projects/1320-sky130mpw5-sramtest/extra_be_checks/1320-test$ ./run_ext
Magic 8.3 revisi…
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## Expected Behavior
I want to convert .lib file to .db file for DC by Synopsys Library Complier.
## Actual Behavior
However,when Library Complier reads sky130_fd_sc_hd__ff_100C_1v65.lib, it repo…
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**Describe the bug**
Silicon Design Module deployment is failing
**To Reproduce**
Steps to reproduce the behavior:
1. Go to [Silicon Design module](https://github.com/GoogleCloudPlatform/rad-lab…