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This issue appears to be independent of the Questa, Python or cocotb versions used.
I have a simple RTL simulation that uses cocotb running on Questa/Modelsim. On the simulation's conclusion I ca…
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I noticed that when I run pytest with pipenv (which is fairly standard), the `run_filename` passed to the simulator is the parent directory of the Python in the virtual environment (e.g. `/home//.loca…
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Hello renode community,
I'm working on risc-v softcore with systemverilog and using a verilator simulator.
I want to integrate my work to renode for further experiments in network side.
I see i…
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Hi! I am working on improving the VIA 6522 shift register implementation in VICE. I'm searching around for reverse engineering details regarding the exact timing of the timer, when it sets the timer 2…
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It seems to be verilog (`vlog`) only, I checked the documentation.
```
INFO cocotb:simulator.py:281 # vcom -mixedsvvh -incr -work some_lib /path/to/cocotb-test/tests/dff.vhdl
INFO cocot…
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It would be nice if the simulator could be selected without setting an env var. Ideally, `cocotb_test.simulator.run` should be updated to accept a `simulator` argument that could select the simulator…
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I tried running the VHDL version of TinyALU and it did not work. The problem seems to be that nothing stimulates the clock in the VHDL design where it does in the Verilog.
I edited my Makefile like…
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# Host Env
* cocotb version = 1.6.0,
* os version = centos7.6 x86_64,
* simulator and version = Questa Sim-64 vsim 10.7c,
* Python version = 3.6.8
## Step 1
[axil_ram](https://github.com/…
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I'm trying to run a simulation of the example adder with a synthesized version of the design that includes a Verilog PDK library file and an SDF annotation file. CVC64 allows for SDF values to be ann…
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Hi,
I have experience in Python, but I am new to Verilog and I am having some problems trying to create a working test. The problem I am having is around the issue of the toplevel. As I didnt find …