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- [x] Compiling [TSVC](https://github.com/UoB-HPC/TSVC_2) benchmark would be a good way to find out if commonly found loop structures are getting vectorized.
- [ ] Instruction scheduling of vectoriz…
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Some instructions have different encodings between RV32 and RV64.
From the RISC-V ISA Specification (20191213), Chapter 24, "RV32I Base Instruction Set":
![image](https://github.com/ThinkOpenly/sa…
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### Describe the bug
https://landscape.riscv.org/card-mode is pulling anyone without a Crunchbase entry under the RISC-V Member Products/Projects category.
### To Reproduce
This was triggered…
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When compiling a minimal RISC-V Sail source into Jib (though I expect this is the same when compiling the emulators) I'm finding that `riscv_sys_control.sail` is dependent on the following files:
-…
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## Quick summary
When I trying to build and package Play! for linux on riscv64 architecture, I got `No SIMD instrinsics available for this platform.`
## System Details
- Operating system: Arch …
qyl27 updated
3 months ago
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I noticed that building the OCaml simulators for sail(-cheri)-riscv takes multiple minutes (in some builds up to 10 minutes per target) after switching to sail built with OCaml 4.14.0 and 4.14.1. Usin…
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https://godbolt.org/z/bhTzz9Tb6
```s
foo():
.cfi_sections .debug_frame
.cfi_startproc
addi sp, sp, -16
.cfi_def_cfa_offset 16
…
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### The problem
Hello, I saw a few posts here that discussed the lack of support for ESP32-C6, presumably because it wasn't officially supported in Arduino or ESP-IDF frameworks but both now do sup…
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Running the testsuite of perl-OpenGL, the test is hanging in an infinite loop inside JIT code. In the JIT code, all subroutine calls are turned into a `auipc ra,0; jalr ra` sequence, so the actual su…
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
In RISC-V, jumps to misaligned instruction addresses should trigger a misaligned fetch …