-
It seems that the iverilog invocation doesn't allow for SystemVerilog support:
https://github.com/google/xls/blob/c330e64365e56439ab9496159aa8664c6cd5eb6a/xls/simulation/simulators/iverilog_simulator…
-
Currently, Windows CI fails to compile Icarus Verilog; since the job times out:
```
Wed, 28 Feb 2024 18:57:22 GMT g++ -shared -Wl,--enable-auto-image-base -o sizer.tgt sizer.o scan_lpms.o scan_lo…
-
Of the given targets, only `doc` and `catalog` appear to exist:
```
cibyr@DESKTOP-36BCE64:~/src/StdCellLib$ make alf
make: *** No rule to make target 'alf'. Stop.
cibyr@DESKTOP-36BCE64:~/src/St…
cibyr updated
5 years ago
-
ExportVerilog is now a pass, and can have other passes scheduled after it. It would be great to change the python bindings to reflect this and remove the hard coded `circt.export_verilog` method.
-
While reading a verilog library with specify-blocks, yosys crashes on constructs such as the following:
```
if (...) (B => Z) = (...);
ifnone (B => Z) = (0, 0);
```
The error message …
-
Converting a block to Verilog that takes a TristateSignal does not work if you also set 'initial_values=True'. The resulting error:
n = None, radix = ''
def _intRepr(n, radix=''):
…
-
**Is your feature request related to a problem? Please describe.**
In the CircuirtVerse we have only a Module export to the Verilog description language.
**Describe the solution you'd like**
The …
-
I would like to use 2 SoC. (e.g one exclusively for WiFi and another exclusively for Data Acquisition) I am able to get 2 Verilog files but am unable to synthesis them due to **Verilog Error: (VERI-12…
-
From VHDL to C, and, if time, from VHDL to Verilog.
adeck updated
10 years ago
-
#### Proposed Behaviour
Generate and use a lookahead map based on entry and exit from routing fabric.
#### Current Behaviour
The existing map lookahead only considers the current wire type and di…