-
I'm trying to build this toolchain for Pulpino, unfortunately I get the following problem on several commits. Is there any combination of Pulpino / ri5cy_gnu_toolchain that works?
Here I'm using Ub…
-
Hello,
I'm trying to import verilog code into migen design as below:
First I created shifter.v:
```verilog
module shifter(
input sck_i,
input sdi_i,
output sdo_o,
input csn_i,
);…
-
When I run it with one of my toplevel files, git gives this. Where is outvTbgenerator.py
$ python /home/local/NDC/ssheikh/.vscode/extensions/truecrab.verilog-testbench-instance-0.0.5/out\vTbgenerat…
-
A big part of writing reliable Verilog designs is specifying things like timing constraints.
The most popular format for constraints is called [SDC - Synopsis Design Constraints](http://www.vlsi-ex…
-
When I try to compile J1B (via `make` in `j1b/swapforth/j1b/verilator`), I get the old error:
```
verilator --l2-name v -Wall -I../verilog/ --cc j1b.v ../verilog/j1.v ../verilog/stack.v --top-modul…
-
[Enter steps to reproduce:]
1. ...
2. ...
**Atom**: 1.50.0 x64
**Electron**: 5.0.13
**OS**: Mac OS X 10.15.6
**Thrown From**: [language-systemverilog](https://github.com/pistoletpierre/langu…
-
BSC can generate a Verilog simulation for a design, using the `bsc_build_vsim_*` scripts in `src/exec/`. These scripts run the Verilog tool (iverilog, Questa, etc) to generate a simulation binary, an…
-
While I understand the code generation with ram support is very experimental;I wanted to ask if you see something wrong with this example that produces the following:
pipeline_schedule.cc:249] Chec…
-
Crucially:
https://github.com/clash-lang/clash-compiler/blob/31857597f103a2a62eb8657a4b7c3360bfbe484c/clash-lib/src/Clash/Backend/Verilog.hs#L751
should read
```
hty = BitVector (start-e…
-
I am trying to use pyverilog with the register files generated with peakRDL-verilog (https://github.com/hughjackson/PeakRDL-verilog) and I am getting the following error.
g++ -I. -MMD -I/usr/loca…