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Hi @themperek @eric-wieser @imphil @marlonjames @ktbarrett
I have a cocotb testbench that is fully functional on version 1.2.0, with drivers, monitors, scoreboard etc.
I am trying to upgrade the…
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Have you seen VUNIT [https://github.com/VUnit/vunit](url)? This might be an interesting integration. It even has file dependency processing.
_Originally posted by @leftink in https://github.com/c…
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I tried deploying the CDK stack with the suggested command
`npx cdk deploy --parameters RepositoryUrl=https://github.com/aws-samples/langchain-agents.git --parameters ProjectName=Langchain-Agents --r…
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**Description**
When I run my simulation, GHDL reports a "bound check failure". I checked the code-line that is reported and to me it looks correct. The line assigns the output of a function to a var…
ghost updated
4 years ago
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> **Describe the bug**
I am a student who started to learn openfpga weeks ago and I don't how to solve the problem. Anyboby can help me?
ERROR 1
Type: SDC file
line: -1
message: syntax error,un…
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host_get_copy_bytes_normal() in host-zephyr.c aligns down copy bytes to DMA specific value:
```
return ALIGN_DOWN(dma_copy_bytes, hd->dma_copy_align);
```
For some frame sizes, this can lead to a …
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Hi,
I've started working with this tool. I tried to convert a simple xgboost tree into VHDL. Conifer is creating the files without a problem, however when I try to import them in Vivado it's a mes…
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I ran Qucs in a old version which I do not know what exactly it was (I installed the snap under Xubuntu 17.10) and everything seemed fine until I tried to run a digital project (entering the schematic…
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## Bug Title
Error writing to memory using test bench files located in cv32e40s/tb/core
### Type
Indicate whether the type of problem you found:
* Functionally incorrect behavior
### Steps to…
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Hi !
This is an awesome project! I came across your project and wanted to implement it in FPGA however I'm a little bit unsure on the manual assignments for Pin Planner in the FPGA. Is there a spe…