ZFTurbo Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA issues

ZFTurbo / Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA

Verilog Generator of Neural Net Digit Detector for FPGA

Apache License 2.0

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issues

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Increase convolutional speed

#34 ECEVLSIWorld opened 1 year ago
0
convert_image_for_testbench.py

#33 ECEVLSIWorld closed 1 year ago
9
Convert_image_for_testbench.py

#32 ECEVLSIWorld closed 1 year ago
0
Fix minor bugs

#31 MaKaRoIIIKa closed 1 year ago
0
SD RAM On DE10 Fpga

#30 HurairaCodes closed 2 years ago
0
The verilog project fails under higher clock frequencies (use PLL frequency multiplication 100MHz), and the FPGA output is not as expected

#29 MisRight opened 2 years ago
0
Questions about the architecture of CNN

#28 kangliyu1 opened 2 years ago
1
some questions about storage data

#27 kangliyu1 opened 2 years ago
2
Some problems with reading verilog code

#26 kangliyu1 closed 2 years ago
4
some questions about project

#25 kangliyu1 closed 2 years ago
3
some question about simulasion

#24 kangliyu1 closed 2 years ago
1
Fixed minor errors

#23 MaKaRoIIIKa closed 2 years ago
0
Some questions about network architecture

#22 kangliyu1 closed 2 years ago
10
On the simulation problem of neuroset's verilog

#21 kangliyu1 closed 2 years ago
3
some question about verilog/code/neuroset

#20 kangliyu1 closed 2 years ago
7
Timing Simulation not working

#19 zee9999 opened 2 years ago
3
The result of testbench doesn't match with the actual result

#18 hithere124 closed 2 years ago
1
About Testbench.v Result

#17 QiQi-OvO closed 2 years ago
5
Terasic DE10-Lite

#16 Bahadiirr opened 3 years ago
1
add arXiv link

#15 alxndrkalinin closed 3 years ago
0
update paper citation

#14 alxndrkalinin closed 3 years ago
0
error when run python code: r05_verilog_generator_neural_net_structure.py

#13 giathinhlenguyen opened 3 years ago
4
How to simulate the generated verilog

#12 ghost opened 4 years ago
30
Fix case mismatch in filename (causes compilation failure in linux).

#11 aaronferrucci closed 4 years ago
0
modules and/or ice40 port?

#10 peepo opened 5 years ago
0
Quartus compilation failing

#9 JonathanKing01 opened 5 years ago
1
改变结构

#8 xw2333 opened 5 years ago
0
Fixed minor errors

#7 MaKaRoIIIKa closed 5 years ago
0
маленькие правки

#6 MaKaRoIIIKa closed 5 years ago
0
cam_proj.out.sdc

#5 hooper888 opened 5 years ago
4
Pin Planner for FPGA

#4 gabrielchin96 opened 5 years ago
6
Different components configure

#3 baogiadoan opened 5 years ago
8
the question of verilog code generator

#2 xw2333 opened 5 years ago
21
How to run those python Codes to generate verilog codes step by step?

#1 pualdelis opened 6 years ago
5