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Hi,
It would be useful to alow to set custom parameter (verilog backend) to signals and ram.
For example with xilinx FPGA : (\* KEEP = "TRUE" *) reg [10:0] myRegister;
Use case :
Last day i had to …
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Hello.
Template substitution does not work as expected, when passing array:
```
from myhdl import *
from math import ceil
def _mem_init_gen(mem):
@instance
def mi():
"""Initi…
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SpinalHDL: 1.10.1
Scala version: 2.12.18
sbt version: 1.9.8
SymbiYosys version: Git 19.02.204
Problem:
- SymbiYosys chokes on "assert(xxx) else begin end"- statements ( maybe not supported? )
…
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http://www.jhauser.us/arithmetic/HardFloat.html
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While I understand the code generation with ram support is very experimental;I wanted to ask if you see something wrong with this example that produces the following:
pipeline_schedule.cc:249] Chec…
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A big part of writing reliable Verilog designs is specifying things like timing constraints.
The most popular format for constraints is called [SDC - Synopsis Design Constraints](http://www.vlsi-ex…
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When I try to compile J1B (via `make` in `j1b/swapforth/j1b/verilator`), I get the old error:
```
verilator --l2-name v -Wall -I../verilog/ --cc j1b.v ../verilog/j1.v ../verilog/stack.v --top-modul…
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[Enter steps to reproduce:]
1. ...
2. ...
**Atom**: 1.50.0 x64
**Electron**: 5.0.13
**OS**: Mac OS X 10.15.6
**Thrown From**: [language-systemverilog](https://github.com/pistoletpierre/langu…
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### 前言
昨天看到有老哥写了[Chisel的difftest接入](8)，心血来潮想试试Verilog怎么接入。
一定要参考[Chisel的difftest接入](8)、[DiffTest Usge](https://github.com/OpenXiangShan/difftest/blob/master/doc/usage.md)这两篇，我算是一点点补充
水平有限，请各位多多指教。
…
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### **SUGGESTION**
Provide links for the books posted under reference
### **STEPS TO REPRODUCE THIS ISSUE**
1. Go to this [link](http://cse14-iiith.vlabs.ac.in/Introduction.html)
2. Click on lis…