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**Which problem is this feature request solving?**
Instance, net, and reg in the VSCode outline use the same icons, making them difficult to distinguish.
This forces me to look at the small prin…
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https://cloudplayer99.github.io/2020/06/18/%E5%8F%AA%E9%9C%80xx%E5%85%83%EF%BC%8C%E4%B8%80%E5%91%A8%E5%AD%A6%E4%BC%9AVerilog%20HDL%EF%BC%8C%E7%9C%8B%E5%88%B0%E8%B5%9A%E5%88%B0%20+qq%20%E5%B0%B1%E8%83%…
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_**Completed installation of vendor files.
Adding Tcl script options from file custom/scripts/gds_import_io.tcl
Migrating GDS files to layout.
Getting GDS file list from /mnt/e/sky130repo/openpdk-g…
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It seems that some of the package are not compatible with the runtime environment present in https://colab.research.google.com/.
Installing the following packages with:
```
!curl -O https://repo…
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Hi all, I'm trying to simulate the project for VC707 (VC707_gen1x8lf64) using Vivado 2015.4. The Vivado runs on Ubuntu 14.04. However, the simulation has errors as following:
ERROR: [VRFC 10-1342] …
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**Type of issue**: bug report
**Impact**: API modification
**Development Phase**: request
**Other information**
When running
litex-boards/litex_boards/targets/sipeed_tang_primer_20k.p…
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Hi, i'm interesting in this project, but is there any materials about the algorithm that this project use to convert rust to verilog? Like papers or others?
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**Project description**
A language server for systemverilog that has been tested to work with coc.nvim, VSCode, Sublime Text 4, emacs, and Neovim
It is a language server for verilog and system ver…
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### Description
Select a data path row, then right click and get a menu to "Show in ..."
![image](https://user-images.githubusercontent.com/2798822/226295495-bf15596b-c2e1-41f1-8a9e-9141fc9f5596.p…
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How to repeat:
1. Run ```$ placement_tool=graywolf qflow gui```
2. Choose ```Technology=osu035```
3. Choose the Verilog file ```map9v3.v```
4. Hit ```Run``` for Preparation, then for Synthesis
…