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For our accelerator design interfaced with Connectal, we've temporarily downgraded our interface to work with DataBusWidth=128 (it used to work with DataBusWidth=256 at some point with some ancient br…
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Hello, is the U500 project for nexys complete? I used the script Makefile.u500nexys4ddrdevkit to generate the mcs file and solidify it into the development board, and successfully generated the bbl.bi…
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I tried to run a simulation of `femtorv32_quark.v` using the Vivado simulator, because I my SoC gets past synthesis well, but gets minimized to nothing during implementation, I do not know what is goi…
jeras updated
2 years ago
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# SymbiFlow Formal Verification
Next semester I am doing an independent study on formal verification and am planning on doing a project involving SymbiFlow. My initial thought is performing formal …
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-look for timing violations
-record build runtime
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Hello, I am using Vivado 2020.2 to compile the au250 model. However, I encountered an error that the IP "cms_subsystem" was not found in the entire file. Can you please advise on how to resolve this i…
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When I used ‘vivado_hls -f script.tcl' , there is an error in the following.
In my mind, you may miss a file that is named 'directives.tcl'.
`INFO: [SYN 201-201] Setting up clock 'default' with a …
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Hi skordal! I really appreciate your work on risc v potato processor. I am having an issue setting up and running the potato processor. I am trying to follow your System-On-Chip Design using the Potat…
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### Issue Description
My original motivation is creating dockerized development environments keeping installations of Xilinx Vivado and tooling. This Package is huge ~100GBs+. Migrating this setup fr…
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I want to document several helper scripts in my documentation. All scripts share for example the `-v` and `-d` option to enable verbosity and debug modes. Unfortunately, the index refers only to one `…