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Consider the two following hardware scenarios:
1) Linux running on x86 w/ FPGA fabric connected via PCIe
2) Linux running on Arm A53 with AXI i/f to FPGA fabric (Think Xilinx Zynq)
How could the …
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Would it be possible to change the bus width size of NastiIO fron 64 bits to 128bits? That would apply to nasti.r.bits.data and nasti.w.bits.data specifically. The purpose is being to perform read and…
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Hello,
I have recently bought an M.2 screamer board and I’m having massive issue when attempting to use PCILeech. I receive an 4,v4.3 meaning the usb connection from my screamer to my second PC is th…
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Bitmain will begin shipping the Z9 Equihash miner soon. Let's use this thread to discuss ASIC resistance: Is it something we want to spend the time/resources to continue, or should we embrace ASICs?…
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It feels like there is a lot of duplication between all the symbiflow (and some non-symbiflow repositories like the Fomu workshop) around getting a nice sphinx setup.
It would be good if there was …
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**Environment**
- OS: Ubuntu 20.04.5 LTS
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- Vitis version: 2021.1
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- Platform: [xilinx_u280_xdma_201920_3]
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- TAPA version: 0.0.20220807.1
Generating VecAdd.xilinx_u2…
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I have this core implemented in a Zynq with a DMA implemented to send and receive data from the FTDI core which is connected to an FT601. However, sending data from the PC to the FPGA does not work, F…
gswdh updated
2 months ago
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### Description
Using the latest ROM_EXT binaries on the `earlgrey_es_sival` branch at
`sw/device/silicon_creator/rom_ext/prodc/binaries/rom_ext_real_prod_signed_slot_a_fpga_cw310.signed.bin`, I …
jettr updated
1 month ago
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Hello, I am very interested in this project, and I have met some problems in my study.
I have instantiated the `ddr3_x16_phy_cust` and `ddr3_rdcal` modules in your Arty S7-50 project, and programme…
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This issue is intended to track progress on Phase 2 of [Calyx Meets the Real World](https://github.com/cucapra/calyx/discussions/1756). This writeup gives great overarching context and what we are wor…