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We should add support to test ready/valid interfaces, including random pressure. Related to this is the discussion here: https://github.com/ucb-bar/chisel-testers2/pull/326
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I am having problems using the AXI VCs in activeHDL 11.1 where I see the the simulator times out from the VUnit watchdog. In ModelSim and GHDL, I do not see the same problem with the AXI VCs. Unfortun…
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### The problem
After a forced shutdown caused by a power blackout, my Home Assistant installation no longer detects the Bluetooth dongle I'm using (ASUS_USB-BT500). The device appears in the hardwar…
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Hello,
Really nice project,
I would like to port to an FPGA board that runs Linux, I am studying the code so far. A few questions I have
1) I understand you send to PWM controller the moto…
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Is it possible to await a specified command index with AXI VVC? I'm trying to do:
```vhdl
axi_read(....);
cmd_idx := get_last_received_cmd_idx(AXI_VVCT, AXI_VVC_IDX);
await_completion(AXI_VVCT, AX…
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The cyclic transfer routines that used to be called by the read functions in the XDMA driver have been broken for a while and have been removed recently.
Those routines are not used by the standard…
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Thanks for the nice tutorial!! Would it be possible to add the `axi_gpio_switches_leds.overlay` that enables the AXI GPIO controller IP core(s) in the design?
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Thank you! Is there a demo showing how to add new peripheral? Such as Gpio.
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I was hoping to find some hours to write something and submit a PR, but it hasn't happened so far, so I'll make an issue instead.
I can recommend pytest based on previous experience https://github.…
asb updated
10 months ago
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I have the axis_stream_fifo setup.
I attempt to read the data and display it in ascii.
I can read some data which should be a counter that I am clocking in, but all I get are zeros and then I get …