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Hi, I'm using a remote server + docker container to run litex. And I can't physically connect any board to the remote server.
Is it possible to do the following:
> 1. use "python3 -m litex_boards.t…
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I am trying to test linux-on-litex-vexriscv on Genesys2 board. When I load the bitstream with command "$ ./make.py --board=genesys2 --cpu-count=4 --load", the command runs but nothing happened on the …
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I saw a blog (https://www.luffca.com/2022/10/linux-tang-primer/) Running Dual-Core RISC-V Linux on Sipeed tang primer board.
Can add official support for Sipeed tang primer board (using Anlogic’s FP…
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- [x] Add/Verify FPGA SRAM programming through openFPGALoader.
- [x] Add/Verify FPGA Flash programming through openFPGALoader.
- [x] Add instructions in README to load FPGA in SRAM.
- [x] Add instr…
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Currently, when we drop down into firmware for illegal instructions, we decode the instruction and if we have an emulation routine, jump to it.
However, this makes it difficult to debug the cause o…
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I successfully got a basic thing running with a single core, no FPU, and BBL this morning. Now I'm trying to make a maxed out version with 4 cores, an fpu, and running at 100MHz. I'll post dts and bit…
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Hi charles,
What is "hit-under-X-misses" does **L1** and **L2 data cache** of NaXRISCV ? like A "hit-under-X-misses" cache will allow X number of misses to be outstanding in the cache before bloc…
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While profiling some of the litex layers, I found that the riscv mtimer is scheduled through openSBI multiple times per alarm interrupt. This isn't ideal, as the openSBI ecall is relatively expensive …
g2gps updated
5 months ago
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# Baremetal RISC-V Renode - Part 1: Blinky - y2kbugger
[https://blog.y2kbugger.com/baremetal-riscv-renode-1.html](https://blog.y2kbugger.com/baremetal-riscv-renode-1.html)