-
Vitis builds have failed since Jan 1, 2022, possibly due to the format of the stored year for the revision number in the builds. Could someone look into this?
-
Hi,
I am trying to run facerec_resnet20 on my custom board image but I got errors due to model fingerprint mismatch.
`dpu_runner_base_imp.cpp:676] CHECK fingerprint fail ! model_fingerprint 0x1000…
-
参考：https://qiita.com/basaro_k/items/e83128c265ae86801bbc
-
The new reference design `MM_2x2` (#147) requires [`cardano.h`](https://github.com/Xilinx/mlir-aie/blob/5f4970c6ffdeb78bda24106d728f447b2cdaeea3/test/reference_designs/MM_2x2/kernel.cc#L8). Based on s…
-
Would like to know where can I find the dpu.xclbin in the pre-build SD image for KV260?
Thanks
-
Hi, de fine licht
It is indeed convenient to use cmake. However, I would like to use "v++ --config" to configure the kernels and allocate storage according to the xilinx tutorial on vitis. I tried …
-
I've tried running Vitis HLS through KDE's application launcher and the terminal. It only shows the loading window briefly and displays this in the terminal:
```
****** Vitis HLS - High-Level Synt…
-
hamming_window.c
C++ on casting float to integer truncate toward to 0 here:
rom_array[i] = (int16_t)(WIN_COEFF_SCALE * real_val);
Guess that correct rounding should be applied instead.
![hamm]…
-
Hi,
We recently upgraded to XRT/Vitis 2022.1. It seems that Xilinx has made a lot of changes to their OpenCL extension APIs, and as a result, FRT cannot be compiled. Here is an excerpt of the erro…
-
Hi Mario, long time. I noticed that only the throughput test between Kernels is involved in the Benchmark design. How should the bandwidth between CPU and FPGA, that is, PCIe bandwidth, be tested? Tha…