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The following can produce a crash:
```scala
circuit Top : %[[
{
"class":"sifive.enterprise.grandcentral.DataTapsAnnotation",
"blackBox":"~Top|DataTap",
"keys":[
{
…
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Currently, we will convert illegal ground connects to partial connects where the RHS is larger than the LHS. However, if a user passes in an aggregate with this property, we need to emit element-wise …
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Now that #2081 has landed, FIRRTL declarations (wire, node, etc.) can have their own symbol through the `inner_sym` attribute. This now opens up the possibility to translate the `DontTouchAnnotation` …
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请列出明细,谢谢!
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I am having a problem with what I assume is a character encoding problem, but I am not sure. If anyone can help me, I would be grateful.
```
[error] Picked up JAVA_TOOL_OPTIONS: -Xmx8G -Xss8M -Djava…
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Platform: macOS 12.4, x86_64
circt commit: be20cdeebf9fcc3c0ca249f89c8913778a3d94f6
Hey all, I'm trying to run `firtool` on the FIRRTL output of a Chisel-based design from my company (which unfort…
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Port Chisel3's [`InjectingTransform`](https://www.chisel-lang.org/api/latest/chisel3/aop/injecting/InjectingTransform.html) which takes the contents of [`InjectStatement` Annotations](https://www.chis…
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In the following, I would expect the wire `test` and module output `value` to have the same value. Instead, `test` is set to a register which is set to a random value, while the module output `value`…
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error message improvement request
SFC:
```
firrtl.passes.CheckFlows$WrongFlow: @[ComposableCache.scala 652:25]: [module ComposableCache] Expression mods_0.io.resp is used as a SinkFlow but ca…
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