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The following error shows up from time to time on the Vendor tools CI, regarding the baselitex test:
```
FAILED: cd /tmpfs/src/github/symbiflow-arch-defs-presubmit-xc7-vendor/build/xc/xc7/tests/so…
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Structure parameter element is used as as condition in ?: operator to parameterize an instance.
```
.AW (ISA.spec.base.E ? 4 : 5),
```
The `AW` parameter is defined as:
```
int unsigned…
jeras updated
2 years ago
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I'd like to use an 2D arrays port:
output [7:0] data_out[0:3];
Is there any example for generating such port definition in myhdl?
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should be easy to add capability to switch between golden/upgrade firmware on stationrc (in the field, upgrade != golden in general).
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Hi, I am trying to simulate the Trivium code using the tb that is present in the repo. After running the python code to generate the .txt files. The simulation is unsuccessful, it gives the error:
ER…
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Nic30 updated
4 years ago
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I want to document several helper scripts in my documentation. All scripts share for example the `-v` and `-d` option to enable verbosity and debug modes. Unfortunately, the index refers only to one `…
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I generated a litex SoC and deployed it to a Digilent Arty using this command:
```
python3 -m litex_boards.targets.digilent_arty --bios-format float --cpu-type femtorv --cpu-variant gracilis --vari…
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Hi,
I intend to use this design to load AIE kernels generated in MLIR. As a first step, I was trying to generate the simple kernel you provide in https://github.com/nqdtan/vck5000_vivado_ulp/blob/202…
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I have a design where I have imported 2 projects that use common custom circuits. The design simulates and executes ok. When I synthesize the design, I get '"XXXXXX". This is not allowed, please make …