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Hi,
I used Q-2020.03-SP1 and when I "make regression" got the assertion fail same as [issue 638](https://github.com/bespoke-silicon-group/bsg_replicant/issues/638) . But when I switched back to O-…
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The make command is
```
make CONFIG=MegaBoomConfig run-binary-hex BINARY=~/tools/rocket-tools/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv VERILATOR_THREADS=8
```
The full veri…
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It would be great if the tester could peek/poke FIRRTL circuits. Also, it would be nice to use it to test IOs which a FIRRTL transform added, which doesn't have a Chisel equivalent.
I'd recommend l…
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I'm working on a class project to apply _systems engineering_ concepts to a real life project. I would like to work on _GHDL_ because I did computer engineering for undergrad and I've done some experi…
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spi_device_csr_mem_rw_with_rand_reset -
fails on master and is blocking PRs
it also fails local runs with seed 2257198085
using xcelium (CI uses vcs)
could you look into this ASAP as it is bl…
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symbol properties' "template" field not rendering correctly in generated Verilog.
See skywater: `pfet_g5v0d10v5` for example.
Template is defined:
```
template="name=M1
L=0.5
W=1
nf=1
mult=1…
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I have setup or1k_marocchino to run on the digilent arty using Litex. See: https://github.com/enjoy-digital/litex/pull/1161
However, linux is not booting. So far I have traced this to go wrong dur…
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The testbench could work on previous code (when not swap the name of mst_ and slv_ )
when I check the result on latest code
Master read function is correct, but it will fail when master write
Fr…
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Thanks for your great works.
I would like to ask you a question.
I have tried a lot of experiments using scale-sim and found that the results with DRAM seem to be wrong.
Total DRAM access count is …
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I was trying to write simultaneously to a file and sim log, but seems this does not work on 4.102 and causes core dump on 4.200.
```
% obj_dir/Vour
Hello World
Segmentation fault (core dumped)
…