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hey sir :
I just start learning axi stuff, when i read pg059-axi-interconnect [xilinx], im confused about 'Avoiding Deadlock Using Single Slave Per ID', i want to know if you implement this function …
omeag updated
3 years ago
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Our current [quant activation tutorial](https://github.com/Xilinx/brevitas/blob/master/notebooks/02_quant_activation_overview.ipynb) does not explain how to use `scaling_per_output_channel=True`, and …
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there are some warning below.
1. WARNING: [VPL 17-301] Failed to get a license for 'ap_opencl'. Explanation: The license feature ap_opencl could not be found.
2. WARNING: [VPL 60-1142] Unabled to re…
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I'm not up to speed on this workstream but I noticed (a while ago) none of the examples in [reference_designs/horizontal_diffusion](https://github.com/Xilinx/mlir-aie/tree/1028fcdc3fe234be37a063d3f47d…
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Hi,
I am trying to use ROS 2 on a target by doing cross-compilation (Xilinx UltraScale +). I want to avoid the usage of Python and the possibility of using C is very interesting. I would like to kn…
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Thank you for this great starting point for MTS designs.
I set up this project on a fresh SD card image (Pynq 3.0.1) for my RFSoC4x2 board, and followed the install instruction.
After power-cycl…
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Commit 588e68db76f0324e414e20e5809e77de1e6b5f26 adds interrupt mapping function call to interrupt enable/disable functions in xscugig.c. This causes race condition when two R5 cores access common GIC …
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I've come to learn that there are one of two ways an interrupt will be triggered when DMAing data from the PL to the PS...
Case 1. Data stream hits a TLAST signal and generates an interrupt based o…
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Hi,
I wanted to experiment with BlackParrot a bit. First, I test using the Xilinx VC707 board the bitstream didn't work, then I simply use the litex_sim with cpu-type = blackparrot, but it didn't w…
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We need to bring the standby power down for the Parallella to make sure people don't burn up the board just by turning it on. Can we try turning on the following features in parallella_defconfig and c…