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I want the Makefile to support env vars to build specific versions of the tools in the toolchain.
For example, YOSYS_VERSION for Yosys.
It would then do git checkout $YOSYS_VERSION
It could be …
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fedora 30 /usr/local/src for default directory
yosys, arachne-pnr, icestorm from repositories
yosys -V
Yosys 0.8 (git sha1 UNKNOWN, gcc 9.0.1 -O2 -fexceptions -fstack-protector-s…
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**Issue by [whitequark](https://github.com/whitequark)**
_Sunday Aug 18, 2019 at 13:54 GMT_
_Originally opened as https://github.com/m-labs/nmigen/issues/172_
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AsyncFIFO specifies a transparent…
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Synthesizing the following example with `ghdl --synth function_test` seems to produce valid output. However, `yosys -m ghdl -p 'ghdl function_test; synth_ice40'` fails with:
```
-- Running command…
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* [ICE40](http://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/IK/iCE40HardwareChecklist.ashx?document_id=47779)
* [SAMD21](https://cdn.sparkfun.com/datasheets/Dev/Arduino/Boards…
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Thanks again to Tristan for working on synthesis. Here are 2 limitations with memories that hits our code base:
1. An initalizer, of the syntax below, causes an internal assert.
2. When a clock…
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Do we require a testbench for the spi_hw? I tried the code with the same ice40 ultraplus board of lattice semiconductor, but my spi was not successful, just wanted to find where I am missing out. Kind…
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The termination degrades Fastino performance and is not needed. See below:
* The termination of the digital traces to the DACs results in digital crosstalk (see #62).
* Empirically, the termination…
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## Steps to reproduce the issue
I have the following code in a file called test.v:
```
module top (hz100, reset, pb, ss7, ss6, ss5, ss4, ss3, ss2, ss1, ss0, left, right, red, green, blue);
i…
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Wow! That was quick Greg!