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It looks like support for multiple variable definitions in a for-loop initializer is incorrect (introduced with d4bb58630efcdfdcfae09bd691561720173a8ffc). I'm trying to use the following syntax (examp…
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Author Name: **Joel Holdsworth**
Original Redmine Issue: 1288 from https://www.veripool.org
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This SystemVerilog code...
```
typedef struct packed {
logic apples;
logic oranges;
…
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The following code contains "Procesural Continuous Assignment" statement (`assign` in an `always` block) which is not synthesizable (at least not by all tools).
```systemverilog
module test (
…
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**Describe the bug**
I want to see my rram module in schematic view. "Schematic view" didn't output an image, while dev tools returned `console.ts:137 [Extension Host] stack trace: RangeError: Maximu…
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Verilator currently uses reference counting for memory management of SystemVerilog class instances (objects). However, SystemVerilog allows cyclical references between objects. Due to this, reference …
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The following code does not compile in iverilog. I believe this is valid systemVerilog code. At least one commercial tool accepts this happily. iverilog seems to be unhappy about the datatype and w…
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This is with a custom `maxOtherSize` (I set it to 10% instead of 5%). Maybe this is the cause?
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Veryl 活用させて頂いております。 質問ばかりで恐縮なのですが。
### キャストについて
型のキャストについて
```
assign a = b as logic;
assign c = d as u32;
```
などはできないのでしょうか?
localparam などで type を作れば問題ないのですが、int にはキャストできたりするようなのでポ…
ryuz updated
2 months ago
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If you know how to plug a custom analyzer tool into your favorite editor to give instant feedback as you type, we need your help. Scripts and/or documentation would all be appreciated.
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May I suggest that you open for "Discussions" in the repository settings?
This would make for a more natural place to discuss issues as your project moves along, and you could possibly ask @MikePop…