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How may we help - what is your question?
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I haven't made as much progress on this as I'd like over the last couple weeks, so creating a feature request issue to keep it on my list and put down what I've thought about so far.
The feature re…
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I'm having some trouble with the simulator, especially with the behavior of `waitSampling{,Where}`. It seems that the registered output signals of my components, only change after very slightly after …
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Cocotb version: 1.4.0
OS: Ubuntu 18.04LTS 64-bit
Python: 3.6 System
Simulator : Icarus Verilog 11.0
I want to know if cocotb makefile can be edited in a way that the hardware is compiled for Ver…
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To finish lowering wire from the FIRRTL dialect to the RTL dialect, the RTL dialect must support vectors of wires.
While FIRRTL seems to have only vectors of wires, Verilog allows n-dimensional wi…
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Hello, a friend and I are working on a CPU (I'm writing the assembler, he the digital design), we are looking to speed up our ALU, currently it runs at around 100khz and while this is very fast for wh…
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Hello!
Thank you for your work! sv2v is a great tool!
I have noticed that some structures remain after a sv2v pass, here is a way to reproduce them on a real open source design:
0. (prerequis…
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Hi, thanks for this wonderful teaching project.
I'd like to understand the scala/Treadle-based simulation engine, as it allows faster prototyping than verilog-based simulation in RocketChip/Chipyar…
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Hello.
I'm studying the development of a QT application where I integrate iVerilog with a simulated hardware maintenance and diagnostics interface, my goal is to have greater control of my projec…
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I'm currently working on a UART, the receiving circuit to be exact. it runs perfectly fine in the Simulator but somehow doesn't when i put it onto my FPGA. (i tested it by slowing the clock down masse…