-
Might as well see how this goes
-
After changing the tty used by hciattach:
```
$ dmesg | grep tty
[ 0.000000] console [tty0] enabled
[ 1.145803] 00:02: ttyS0 at I/O 0x3f8 (irq = 202, base_baud = 115200) is a 16550A
$ git diff
…
-
@cerna
https://github.com/machinekit/mksocfpga/pull/115/checks?check_run_id=1294764215
AFAIK someone pulled the plug on the old build system a while ago and
someone is yet to place in the replac…
-
Hello All,
I have a **xilinx ZCU102 board.**
I just have two questions:
1. This project is pretty old. Has there been no update in bitcoin code in last 11 years? I am asking because ethereu…
-
So this chip is looking increasingly interesting. And I am starting to understand it better. Right now my attention is on the Compiler branch, Altera version, because that looks the most recent. It …
-
Trying to port this to 20.1 toolchain, using hints from cyclone5 dev kit instructions. I am able to get the sof and uboot compiled and working, but I am having problems with the linux kernel devicetre…
-
I am trying to add the top level in a quartus project but many hdl files are missing from the core dir that the top level calls out.
-
Hello everyone,
I am interested in creating a SoC with 2 cores and a custom communication between them (UART or something else). But reading the BaseSoC implementation, I see no trick that I could …
-
Per user report from https://community.platformio.org/t/sipeed-rv-debugger-lite/19784.
The Lite version seems to be very close to the normal version listed at https://docs.platformio.org/en/latest/…
-
Hello,
I tested the `vhdl uart` example search string. It lists all repositories containing `uart` in the name.
We are providing a big IP core library called [PoC Library](https://github.com/VLSI-ED…