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Hi,
So I've recently tried this on a Rpi4 with the idea to remote debug a Arty-A7 over the network from Vivado 2024.1.2
(since the xilinx tools aren't built for the ARM64)
It does build and run, …
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As asked in twitter to post ideas, this is mine: to be able to run it without the actual hardware
For example:
-Add dummy peripherals to run it on similar hardware that lacks the ADC (i.e. the Acorn…
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The Digilent Arty A7 board is an reasonable cheap, fairly large, modern and extremely common FPGA development board.
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this shouldn't happen:
```
2:43:05 PM: piview: NoArty
2:43:09 PM: piview: ArtyWire
```
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There are quite a few Ethernet MAC cores, but mostly in Verilog. I've a project written in VHDL, use GHDL, and therefore looked for a core written in VHDL, and found this project.
The core was tested…
wfjm updated
5 months ago
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following the steps on:
https://github.com/CarlFK/pici/wiki/Getting-Started#linux-litex
Sometimes it works, sometimes it gets stuck at:
Fetching from: UDP/6069
(no ascii spinner)
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It seems weird that we are using the Digilent Basys OpenOCD configuration file with the Arty board. I'm guessing it is because they are "programmer" compatible?
https://github.com/SymbiFlow/symbifl…
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If this addressed by a PR in flight, just close this.
I'm going through the examples at https://symbiflow-examples.readthedocs.io/en/latest/building-examples.html .
After the counter example is …
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i connected the board and I got this issue after running ./make.py --board=arty --…
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First, we thank you for your impressive work. We would like to reproduce your work on our Artix A7 board.
However, we are not able to do reproduce it as we are getting the below error. Can you pleas…