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I really like teroshdl and wanted to ask if you had considered supporting hdlmake projects (see https://hdlmake.readthedocs.io/en/master/)
It would be really nice to not have to also create a Teros…
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Without having checked this myself, I believe there is Python code in either [HDLMake](http://www.ohwr.org/projects/hdl-make) or [VUnit](https://github.com/LarsAsplund/vunit) for parsing Verilog/VHDL…
olofk updated
7 years ago
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Hi! I am trying to implement the demo on my zybo board, but when loading all the files there are missing modules.
I find that the following modules are missing: sawtooth, console and atlpll_component…
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I wasn't sure how else to communicate with you, as I couldn't find an email address.
Have you seen the project fpgalink. It has utitlies and drivers for easily communicating with many different board…
ghost updated
11 years ago
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Sameer , thanks for the great project.
I am relatively new to Verilog and FPGA development, and I find your work in this field particularly inspiring.
Currently, I am encountering some challenge…
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Hi @sameer,
Firstly, thank you for doing all this work to get a working mipi-hdmi interface on the mkr vidor. I'm new to FPGA's and have been using this board to test some basic logic gate examples…
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The idea is to plot a dependency graph for the given core/system
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Hi @eine. I was checking the categories and they seem ok from a high abstraction level. I mean, they catch almost any possibility in the first part of the category. Maybe we will need to add more sub-…
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Coming from rodrigomelo9/FOSS-for-digital-HW-design#1
> Regards https://github.com/eine/vhdl-cfg, I thought about something similar between PyFPGA and others, such as edalize, hdlmake, tsfpga, and …
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As of now, if specified in a recipe, make.py iterates over all steps for every source file specified. This is usually not wanted behaviour. Example: we need to do some tasks only at the start of the t…