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**Describe the bug**
When multiple ICE40 instances on the same SPI master are enabled the build will fail, as there will be multiple instances of the same pinctrl-config object within fpga_ice40.c.
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The **Error Message** i get is
> own_periphs/uart/UART_1.v:1: ERROR: Re-definition of module `$abstract\uart_clk_div_17_1'!
When i try to instantiate multiple of the same cores, in the **Target …
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The problem seems to be in the space character escaping of the iverilog command.
To reproduce
1. Install all apio packges ``apio packages --install``
2. renamed ``Users/user/.apio/packages`` t…
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David
is ice40 permanently stalled?
I do appreciate you are heavily committed on other open source initiatives!!
have potential interest and/or project, any chance of a headsup?
thanks ag…
peepo updated
2 years ago
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When building with nextpnr-ice40 in version .9 and .10 I get warnings such as:
"Warning: unmatched constraint 'clk_in' (on line 5)" for each set_io line in the .pcf.
You can still build and upload f…
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## Introduction
Currently it is not possible to have multiple ICE40 on the same SPI bus, as described in #77983. The reason for this is the necessity in some cases to do some bitbanging instead of …
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devel@pi5-70:~/pico-ice/my-new-pico-ice-firmware/ice_makefile_verilator_counter $ make
/usr/local//bin/yosys -q -p "read_verilog -sv ice40.sv top.sv; synth_ice40 -top ice40 -json gateware.json"
Warn…
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I ran into a few problems when following the guide "Programming the iCE40" more specifically the "Using APIO" section on the website.
Maybe they are because I'm working on a Mac (Intel Version)
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We are working with NuttX from about 2016 year in university and industrial projects and we have contributed more drivers over years. For ESP32C3, we have contributed CAN/TWAI driver in past and @jano…
ppisa updated
2 months ago
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Would like to support both a bsv and vhdl flow here. I have little experience with the internals here but with some work I think we can get this going.
We'd want to support both ICE40 and ECP5 devi…